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INTEGRATED CIRCUITS
SA7025 Low-voltage 1GHz fractional-N synthesizer
Product specification IC17 Data Handbook 1996 Aug 6
Philips Semiconductors
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
DESCRIPTION
The SA7025 is a monolithic low power, high performance dual frequency synthesizer fabricated in QUBiC BiCMOS technology. Featuring Fractional-N division with selectable modulo 5 or 8 implemented in the Main synthesizer to allow the phase detector comparison frequency to be five or eight times the channel spacing. This feature reduces the overall division ratio yielding a lower noise floor and faster channel switching. The phase detectors and charge pumps are designed to achieve phase detector comparison frequencies up to 5MHz. A triple modulus prescaler (divide by 64/65/72) is integrated on chip with a maximum input frequency of 1.04GHz. Programming and channel selection are realized by a high speed 3-wire serial interface.
PIN CONFIGURATION
DK Package
CLOCK DATA STROBE VSS RFIN RFIN VCCP REFIN RA AUXIN VDD TEST LOCK RF RN VDDA PHP PHI VSSA PHA
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
FEATURES
* Operation up to 1.04GHz * Fast locking by "Fractional-N" divider * Auxiliary synthesizer * Digital phase comparator with proportional and integral charge
pump output
SR00600
* High speed serial input * Low power consumption * Programmable charge pump currents * Supply voltage range 2.7 to 5.5V * Excellent input sensitivity: VRF_IN = -20dBm
APPLICATIONS
Figure 1. Pin Configuration
* NADC (North American Digital Cellular) * PDC (Personal Digital Cellular) * Cellular radio * Spread-spectrum receivers
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Shrink Small Outline Package (SSOP) TEMPERATURE RANGE -40 to +85C ORDER CODE SA7025DK DWG # SOT266-1
ABSOLUTE MAXIMUM RATINGS
SYMBOL V VIN TSTG TA PARAMETER Supply voltage, VDD, VDDA, VCCP Voltage applied to any other pin Storage temperature range Operating ambient temperature range RATING -0.3 to +6.0 -0.3 to (VDD + 0.3) -65 to +150 -40 to +85 UNITS V V C C
NOTE: Thermal impedance (JA) = 117C/W. This device is ESD sensitive.
1996 Aug 6
2
853-1786 17157
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
PIN DESCRIPTIONS
Symbol CLOCK DATA STROBE VSS RFIN RFIN VCCP REFIN RA AUXIN PHA VSSA PHI PHP VDDA RN RF LOCK TEST VDD Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Serial clock input Serial data input Serial strobe input Digital ground Prescaler positive input Prescaler negative input Prescaler positive supply voltage. This pin supplies power to the prescaler and RF input buffer Reference divider input Auxiliary current setting; resistor to VSSA Auxiliary divider input Auxiliary phase detector output Analog ground Integral phase detector output Proportional phase detector output Analog supply voltage. This pin supplies power to the charge pumps, Auxiliary prescaler, Auxiliary and Reference buffers. Main current setting; resistor to VSSA Fractional compensation current setting; resistor to VSSA Lock detector output Test pin; connect to VDD Digital supply voltage. This pin supplies power to the CMOS digital part of the device Description
1996 Aug 6
3
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
BLOCK DIAGRAM
CLOCK DATA STROBE SERIAL INPUT + PROGRAM LATCHES
VDD
VSS EM FB 2 RFIN RFIN 64/65/72 PRESCALER MAIN DIVIDERS PR 2 NM1 12
NM2 NM3 8
FB FMOD NF 3 PRESCALER MODULUS CONTROL RF FRD CN RN
FRACTIONAL ACCUMULATOR
TEST
EM MAIN PHASE DETECTOR 2
8
NORMAL OUTPUT CHARGE PUMP CL
PHP SPEED-UP OUTPUT CHARGE PUMP
SM 2 NR VCCP EM+EA MAIN REFERENCE SELECT
2
12 CK 4 INTEGRAL OUTPUT CHARGE PUMP PHI
REFIN
REFERENCE DIVIDER
/2
/2
/2
SA 2 AUXILIARY REFERENCE SELECT EA PA EA 12 NA AUXILIARY PHASE DETECTOR 2
RA
AUXILIARY OUTPUT CHARGE PUMP
PHA
LOCK AUXIN 1/4 PRESCALER AUXILIARY DIVIDER
VDDA
VSSA
SR00601
Figure 2. Block Diagram
1996 Aug 6
4
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
DC ELECTRICAL CHARACTERISTICS
VDD = VDDA = VCCP = 3V; TA = 25C, unless otherwise specified. SYMBOL VSUPPLY ISTANDBY IAUX IMAIN ITOTAL VIH VIL VOL VOH PARAMETER Recommended operating conditions Total standby supply currents Operational supply currents Operational supply currents Operational supply currents High level input voltage range Low level input voltage range Output voltage LOW Output voltage HIGH Setting current range for any setting reg g y g sistor Output voltage range IRA = -62.5A; VPHA = VDDA/213 IRA = -25A; VPHA = VDDA/2 IRA = -62.5A2, 13 VDDA = 3V, IRA = 25A VDDA = 5V, IRA = 62.5A IRN = -62.5A; VPHP = VDDA/213 IRN = -25A; VPHP = VDDA/2 IRN = -62.5A2, 13 VDDA = 3V, IRA = 25A VDDA = 5V, IRA = 62.5A IRN = -62.5A; VPHP = VDDA/213 IRN = -25A; VPHP = VDDA/2 IRN = -62.5A2, 13 VDDA = 3V, IRA = 25A VDDA = 5V, IRA = 62.5A IRN = -62.5A; VPHI = VDDA/213 IRN = -25A; VPHI = VDDA/2 IRN = -62.5A2, 13 VDDA = 3V, IRA = 25A VDDA = 5V, IRA = 62.5A IRF = -62.5A;FRD = 1 to 713 IRF = -25A;FRD = 1 to 7 5 -625 -250 -400 -180 4.4 1.75 5.5 2.2 2 2.20 0.85 2.75 1.1 2 440 175 550 220 2 IO = 2mA IO = -2mA 2.7V < VDDA < 5.5V 4.5V < VDDA < 5.5V 0.7 400 160 500 200 2 VDD-0.4 25 62.5 VDDA-0.8 600 240 6 50 65 660 265 6 50 65 3.30 1.35 6 250 300 6.6 2.65 8 500 600 -250 -100 TEST CONDITIONS VCCP = VDD, VDDA VDD EM = EA = 0, IRN = IRF = IRA = 0 EM = 0, EA = 1 EM = 1, EA = 0 EM = EA = 1 0.7xVDD 0 LIMITS MIN 2.7 50 3.5 5.5 7.5 VDD 0.3xVDD 0.4 TYP MAX 5.5 500 UNITS V A mA mA mA V V V V
Operational supply currents: I = IDD + ICCP + IDDA; IRN = 25A, IRA = 25A, (see Note 5)
Digital inputs CLK, DATA, STROBE
Digital outputs LOCK
Charge pumps: VDDA = 3V / IRX = 25A or VDDA = 5V / IRX = 62.5A, VPHX in range, unless otherwise specified. (See Note 16) |IRX| VPHOUT A V
Charge pump PHA |IPHA| DI PHP_A | I PHP_A| IPHA_M Output current PHA Relative output current variation PHA Output current matching PHA pump A % A
Charge pump PHP, normal mode1, 4, 6 VRF = VDDA |IPHP_N| DI PHP_N I PHP_N IPHP_N_M Output current PHP Relative output current variation PHP Output current matching PHP g normal mode A % A
Charge pump PHP, speed-up mode 1, 4, 7 VRF = VDDA |IPHP_S| S DI PHP_S I PHP_S IPHP_S_M S Output current PHP Relative output current variation PHP Output current matching PHP g speed-up mode mA % A
Charge pump PHI, speed-up mode 1, 4, 8 VRF = VDDA |IPHI| DI PHI I PHI IPHI_M Output current PHI Relative output current variation PHI Output current matching PHI pump mA % A
Fractional compensation PHP, normal mode 1, 9 VRN = VDDA, VPHP = VDDA/2 IPHP_F_N Fractional compensation output current PHP vs FRD3 nA
1996 Aug 6
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
DC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN -3.35 -1.35 -20 IRF = -62.5A;FRD = 1 to 713 IRF = -25A;FRD = 1 to 7 -5.4 -2.15 -4.0 -1.6 TYP -2.0 -1.0 MAX -1.1 -0.5 20 -2.6 -1.05 UNITS
Fractional compensation PHP, speed up mode 1, 10 VPHP = VDDA, VRN = VDDA IPHP_F_S S Fractional compensation output current PHP vs FRD3 Pump leakage Fractional compensation PHI, speed up mode 1, 11 VPHP = VDDA/2, VRN = VDDA IPHI_F Fractional compensation output current PHI vs FRD3 Output leakage current PHP; normal mode1 Output leakage current PHI; normal mode1 Output leakage current PHA A IRF = -62.5A;FRD = 1 to 713 IRF = -25A;FRD = 1 to 7 A nA
Charge pump leakage currents, charge pump not active IPHP_L IPHI_L IPHA_L VPHP = 0.7 to VDDA - 0.8 VPHI = 0.7 to VDDA - 0.8 VPHA = 0.7 to VDDA - 0.8 0.1 0.1 0.1 10 10 10 nA nA nA
AC ELECTRICAL CHARACTERISTICS
VDD = VDDA = VCCP = 3V; TA = 25C; fRF_IN = 1GHz, input level = -20dBm; unless otherwise specified. Test Circuit, Figure 4. The parameters listed below are tested using automatic test equipment to assure consistent electrical characteristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters. SYMBOL Main divider fRF_IN VRF_IN Input signal frequency Input sensitivity Direct coupled input14 1000pF input coupling 1040MHz 2.7 < VDD and VDDA < 5.5V 2.7 < VDD and VDDA < 4.5V 2.7 < VDD and VDDA < 5.5V 2.7 < VDD and VDDA < 4.5V 500 300 100 3 0 4.5V VDDA 5.5V 4.5V VDDA 5.5V 0 0 0 200 100 3 10 30 30 30 B, C, D, E words FVCO = 1030MHz 30 300 600 50 150 30 40 mVP-P k pF MHz ns ns ns MHz -20 1.04 1.04 0 25 30 GHz dBm PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNITS
Reference divider (VDD = VDDA = 3V or VDD = 3V / VDDA = 5V) fREF_IN VREF_IN ZREF_IN Input signal frequency Input signal range, AC coupled range Reference divider input impedance15 MHz mVP-P k pF
Auxiliary divider Input signal frequency fAUX_IN PA = "0", prescaler enabled Input signal frequency PA = "1", prescaler disabled VAUX_IN ZAUX_IN Input signal range, AC coupled Auxiliary divider input impedance
Serial interface15 fCLOCK tSU tH tW Clock frequency Set-up time: DATA to CLOCK, CLOCK to STROBE Hold time; CLOCK to DATA Pulse width; CLOCK Pulse width; STROBE Main loop residual FM
In-Loop Performance17 VDDA = 5V, VDD = 2.7V RMM Hz
1996 Aug 6
6
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
AC ELECTRICAL CHARACTERISTICS (continued)
SYMBOL PARAMETER TEST CONDITIONS A word, PR = `01' tSW Pulse width STROBE width; A word, PR = `10'
1 f VCO
LIMITS MIN TYP MAX 1 @ (NM2 @ 65) ) t W f VCO
@ [(NM2 @ 65) ) (NM3 ) 1) @ 72] ) t W
UNITS
ns
NOTES: 1. When a serial input "A" word is programmed, the main charge pumps on PHP and PHI are in the "speed up mode" as long as STROBE = H. When this is not the case, the main charge pumps are in the "normal mode". 2. The relative output current variation is defined thus: DI OUT (I * I 1) +2@ 2 ; with V1 = 0.7V, V2 = VDDA - 0.8V (see Figure 3). |(I 2 ) I 1)| I OUT 3. FRD is the value of the 3 bit fractional accumulator. 4. Monotonicity is guaranteed with CN = 0 to 255. 5. Power supply current measured with VDD = VCCP = 3V, VDDA = 5V, fRF IN = 915.99MHz, XTAL at 21.36MHz, AUX at 85.92MHz (PA = `0'), Main comp frequency = 240kHz, Auxiliary comp frequency = 120kHz, CN = 160, CL = 0, CK = 0. Internal registers NM1 = 52, NM2 = 0, NM3 = 4, PR = `10', SM = `00', SA = `01', NA = 179, NF = 5, FMOD = 8, NR = 89, PA = 0, IRN = IRA = IRF = 25A, lock condition, normal mode. Operational supply current = IDDA + IDD + ICCP. 6. Specification condition: CN = 255 7. Specification conditions: 1) CN = 255; CL = 1, or 2) CN = 75; CL = 3 8. Typical output current | IPHI | = -IRN x CN x 2(CL+1) x CK/32: 1) CN = 160; CL = 3; CK = 1, or 2) CN = 160; CL = 2; CK = 2, or 3) CN = 160; CL = 1; CK = 4, or 4) CN = 160; CL = 0; CK = 8 9. Any RFD, CL = 1 for speed-up pump. The integral pump is intended for switching only and the fractional compensation is not guaranteed. 10. Specification conditions: FRD = 1 to 7; CL = 1. 11. Specification conditions: 1) FRD = 1 to 7; CL = 1; CK = 2, or 2) FRD = 1 to 7; CL = 2; CK = 1. 12. The matching is defined by the sum of the P and the N pump for a given output voltage. 13. Limited analog supply voltage range 4.5 to 5.5V. 14. For fIN < 50MHz, low frequency operation requires DC-coupling and a minimum input slew rate of 32V/s. 15. Guaranteed by design. 16. Close in noise for the charge pumps is tested on a sample basis in a typical application in order to eliminate parts outside the normal distribution. 17. FXTAL = 14.4MHz, VXTAL = 500mVP-P, comparison frequency = 200kHz, Loop bandwidth = 5kHz, Audio filter = 300Hz to 15kHz.
1996 Aug 6
7
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
CURRENT I2
I1
V1
V2
VOLTAGE
I2
I1
SR00602
Figure 3. Relative Output Current Variation
22nF CLOCK 1 CLOCK 10F VDD TEST 20 VDD
DATA
2
DATA
19
TEST
STROBE
3
STROBE
LOCK
18
LOCK RF 150k
22nF 50 RFIN
10K
4
VSS RFIN RFIN VCCP REFIN RA
RF
17 150k RN
SA7025
RN 16
5 22nF 50
10F 22nF VDDA PHP 15 1k 14 100 13 VPH VDD
RFIN 10F VCCP 22nF REFIN 50 22nF AUXIN 50 150k 22nF
6
A
7
P
VPHI
8
PHI
9
VSSA PHA
12 1k 11 VPH
10
AUXIN
A
SR00603
Figure 4. Test Circuit
1996 Aug 6
8
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
AC TIMING CHARACTERISTICS
DATA
D0
D1 tH
D22, D30
D23, D31
D0
tSU
tSU
50%
CLOCK FIRST CLOCK LAST CLOCK tSU FIRST CLOCK
STROBE CLOCK ENABLED SHIFT IN DATA CLOCK DISABLED STORE DATA
tW
tSW
CLOCK STROBE (B, C, D, E) WORDS
50%
STROBE (A WORD)
50%
SR00604
Figure 5. Serial Input Timing Sequence
FUNCTIONAL DESCRIPTION Serial Input Programming
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program all counter ratios, DACs, selection and enable bits. The programming data is structured into 24 or 32 bit words; each word includes 1 or 4 address bits. Figure 5 shows the timing diagram of the serial input. When the STROBE = L, the clock driver is enabled and on the positive edges of the CLOCK the signal on DATA input is clocked into a shift register. When the STROBE = H, the clock is disabled and the data in the shift register remains stable. Depending on the 1 or 4 address bits the data is latched into different working registers or temporary registers. In order to fully program the synthesizer, 4 words must be sent: D, C, B and A. Figure 6 and Table 1 shows the format and the contents of each word. The E word is for testing purposes only. The E (test) word is reset when programming the D word. The data for CN and PR is stored by the B word in temporary registers. When the A word is loaded, the data of these temporary registers is loaded together with the A word into the work registers which avoids false temporary main divider input. CN is only loaded from the temporary registers when a short 24 bit A0 word is used. CN will be directly loaded by programming a long 32 bit A1 word. The flag LONG in the D word determines whether A0 (LONG = "0") or A1 (LONG = "1") format is applicable. The A word contains new data for the main divider.
values. Therefore, the new A word will be correctly loaded provided that the STROBE signal has been at an active high value for at least a minimum number of VCO input cycles at RFIN or RFIN.
t_strobe_min + t_strobe_min + 1 (NM @ 65) ) t for PR + `01 2 W f VCO 1 [NM @ 65 ) (NM ) 1) @ 72] ) t for PR + `10 2 3 W f VCO
Programming the A word means also that the main charge pumps on output PHP and PHI are set into the speed-up mode as long as the STROBE is H.
Auxiliary Divider
The input signal on AUX_IN is amplified to logic level by a single-ended CMOS input buffer, which accepts low level AC coupled input signals. This input stage is enabled if the serial control bit EA = "1". Disabling means that all currents in the input stage are switched off. A fixed divide by 4 is enabled if PA = "0". This divider has been optimized to accept a high frequency input signal. If PA = "1", this divider is disabled and the input signal is fed directly to the second stage, which is a 12-bit programmable divider with standard input frequency (40MHz). The division ratio can be expressed as: if PA = "0": N = 4 x NA if PA = "1": N = NA; with NA = 4 to 4095
Main Divider Synchronization
The A word is loaded only when a main divider synchronization signal is also active in order to avoid phase jumps when reprogramming the main divider. The synchronization signal is generated by the main divider. The signal is active while the NM1 divider is counting down from the programmed value. The new A word will be loaded after the NM1 divider has reached its terminal count; also, at this time a main divider output pulse will be sent to the main phase detector. The loading of the A word is disabled while the NM2 or NM3 dividers are counting up to their programmed 1996 Aug 6 9
Reference Divider
The input signal on REF_IN is amplified to logic level by a single-ended CMOS input buffer, which accepts low level AC coupled input signals. This input stage is enabled by the OR function of the serial input bits EA and EM. Disabling means that all currents in the input stage are switched off. The reference divider consists of a programmable divider by NR (NR = 4 to 4095) followed by a three bit binary counter. The 2 bit SM register (see Figure 7) determines which of the 4 output pulses is selected as the main
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
phase detector input. The 2 bit SA register determines the selection of the auxiliary phase detector signal.
Main Divider
The differential inputs are amplified (to internal ECL logic levels) and provide excellent sensitivity (-20dBm at 1GHz) making the prescaler ideally suited to directly interface to a VCO as integrated on the SA620 RF gain stage, VCO and mixer device. The internal triple modulus prescaler feedback loop FB controls the selection of the divide by ratios 64/65/72, and reduces the minimum system division ratio below the typical value required by standard dual modulus (64/65) devices. This input stage is enabled when serial control bit EM = "1". Disabling means that all currents in the prescaler are switched off. The main divider is built up by a 12 bit counter plus a sign bit. Depending on the serial input values NM1, NM2, NM3, and the prescaler select PR, the counter will select a prescaler ratio during a number of input cycles according to Table 2 and Table 3. The loading of the work registers NM1, NM2, NM3 and PR is synchronized with the state of the main counter, to avoid extra phase disturbance when switching over to another main divider ratio as explained in the Serial Input Programming section. At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented with NF. The
accumulator works modulo Q. Q is preset by the serial control bit FMOD to 8 when FMOD = "1". Each time the accumulator overflows, the feedback to the prescaler will select one cycle using prescaler ratio R2 instead of R1. As shown above, this will increase the overall division ratio by 1 if R2 = R1 + 1. The mean division ratio over Q main divider will then be NQ + N ) NF Q Programming a fraction means the prescaler with main divider will divide by N or N + 1. The output of the main divider will be modulated with a fractional phase ripple. This phase ripple is proportional to the contents of the fractional accumulator FRD, which is used for fractional current compensation.
Phase Detectors
The auxiliary and main phase detectors are a two D-type flip-flop phase and frequency detector shown in Figure 8. The flip-flops are set by the negative edges of output signals of the dividers. The rising edge of the signal, L, will reset the flip-flops after both flip-flops have been set. Around zero phase error this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or deadband around zero phase error. The flip-flops drive on-chip charge pumps. A source current from the charge pump indicates the VCO frequency will be increased; a sink current indicates the VCO frequency will be decreased.
1996 Aug 6
10
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
MSB LAST IN WORD D31
LSB D0 FIRST IN
NM2 A1 0 NF NM1 NM3 NM2 CN
D23
D0
NM2 A0 0 NF NM1 NM3 NM2
PR = "01"
PR = "10"
B
1
0
00
0
0
00
CN
CK
CL
PR
C
1
0
01
NA
P A
0
D
1
0
10
NR
SM
E M
SA
FL E MO A ON DG
E
1
1
11 0
00
TT 1 0
0
D23 ADDRESS BITS TEST BITS
D0
SR00605
Figure 6. Serial Input Word Format
Current Settings
The SA7025 has 3 current setting pins: RA, RN and RF. The active charge pump currents and the fractional compensation currents are linearly dependent on the current connected between the current setting pin and VSS. The typical value R (current setting resistor) can be calculated with the formula:
R+ V DDA * 0.9 * 150 IR IR
|I PHA| + 8 @ I RA
Main Output Charge Pumps and Fractional Compensation Currents
The main charge pumps on pin PHP and PHI are driven by the main phase detector and the current value is determined by the current at pin RN and via a number of DACs which are driven by registers of the serial input. The fractional compensation current is determined by the current at pin RF, the contents of the fractional accumulator FRD and a number of DACs driven by registers from the serial input. The timing for the fractional compensation is derived from the reference divider. The current is on during 1 input reference cycle before and 1 cycle after the output signal to the phase comparator. Figure 9 shows the waveforms for a typical case.
The current can be set to zero by connecting the corresponding pin to VDDA.
Auxiliary Output Charge Pumps
The auxiliary charge pumps on pin PHA are driven by the auxiliary phase detector and the current value is determined by the external resistor RA at pin RA. The active charge pump current is typically:
1996 Aug 6
11
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
Table 1. Function Table
Symbol NM1 NM2 NM3 PR Bits 12 8 if PR = "01" 4 if PR = "10" 4 if PR = "10" 2 Function Number of main divider cycles when prescaler modulus = 64* Number of main divider cycles when prescaler modulus = 65* Number of main divider cycles when prescaler modulus = 72* Prescaler type in use PR = "01": modulus 2 prescaler (64/65) PR = "10": modulus 3 prescaler (64/65/72) Fractional-N increment Fractional-N modulus selection flag "1": modulo 8 "0": modulo 5 A word format selection flag "0": 24 bit A0 format "1": 32 bit A1 format Binary current setting factor for main charge pumps Binary acceleration factor for proportional charge pump current Binary acceleration factor for integral charge pump current Main divider enable flag Auxiliary divider enable flag Reference select for main phase detector Reference select for auxiliary phase detector Reference divider ratio Auxiliary divider ratio Auxiliary prescaler mode: PA = "0": divide by 4 PA = "1": divide by 1
NF FMOD
3 1
LONG
1
CN CL CK EM EA SM SA NR NA PA
8 2 4 1 1 2 2 12 12 1
*Not including reset cycles and Fractional-N effects.
MAIN SELECT SM = "00" SM = "01" SM = "10" SM = "11" REFERENCE INPUT DIVIDE BY NR /2 /2 /2 AUXILIARY SELECT SA = "11" SA = "10" SA = "01" SA = "00" AUXILIARY PHASE DETECTOR MAIN PHASE DETECTOR
SR00606
Figure 7. Reference Divider
Table 2. Prescaler Ratio
The total division ratio from prescaler to the phase detector may be expressed as: if PR = "01" if PR = "10" N = (NM1 + 2) x 64 + NM2 x 65 N' = (NM1 + 1) x 64 + (NM2 + 1) x 65 (*) N = (NM1 + 2) x 64 + NM2 x 65 + (NM3 + 1) x 72 N' = (NM1 + 1) x 64 + (NM2 + 1) x 65 + (NM3 + 1) x 72 (*) (*) When the fractional accumulator overflows the prescaler ratio = 65 (64 + 1) and the total division ratio N' = N + 1
1996 Aug 6
12
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
Table 3. PR Modulus
PR 01 10 Modulus Prescaler NM1 2 3 12 12 Bit Capacity NM2 8 4 NM3 - 4 |I PHI| + I RNCN (2 CL)1) CK 32 I RF FRD (2 CL)1) CK 128 In "speed-up mode" the current in output PHI is: I PHI_S + I PHI ) I PHI_comp where:
When the serial input A word is loaded, the output circuits are in the "speed-up mode" as long as the STROBE is H, else the "normal mode" is active. In the "normal mode" the current output PHP is: I PHP_N + I PHP ) I PHP_comp where: |I PHP| + CN @ I RN 32 :charge pump current I RF :fractional comp. 128 current
|I PHI_comp| +
Figure 9 shows that for proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. This means that the current setting on the input RN, RF is approximately: (Q @ f VCO) I RN + I RF (3 @ CN @ F INR) where: Q= fVCO = fINM x N, FINR = fractional-N modulus input frequency of the prescaler input frequency of the reference divider
|I PHP_comp| + FRD @
The current in PHI is zero in "normal mode". In "speed-up mode" the current in output PHP is: I PHP_S + I PHP ) I PHP_comp |I PHP| + CN @ I RN (2 CL)1 ) 1) 32 FRD @ I RF (2 CL)1 ) 1) 128
PHI pump is meant for switching only. Current and compensation are not as accurate as PHP.
|I PHP_comp| +
L REF_IN REFERENCE DIVIDER
"1" R
D C R
Q VDDA
P
P-TYPE CHARGE PUMP
"1" AUX/MAIN DIVIDER
D C
R
PH
X Q N
N-TYPE CHARGE PUMP
VSSA REF_IN L
R X P N IP
H
SR00607
Figure 8. Phase Detector Structure with Timing
1996 Aug 6
13
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
REFERENCE R
TIME
MAIN N VCO CYCLES N N N+1 N N+1
DETECTOR OUTPUT 2 CONTENTS ACCUM. FRACTIONAL COMPENSATION CURRENT 4 1 3 0
PULSE-WIDTH MODULATION
mA OUTPUT ON PHP, PHI A
PULSE-LEVEL MODULATION
SR00608
Figure 9. Waveforms for NF = 2, Fraction = 0.4
Lock Detect
The output LOCK is H when the auxiliary phase detector AND the main phase detector indicates a lock condition. The lock condition is defined as a phase difference of less than +1 cycle on the reference input REF_IN. The lock condition is also fulfilled when the relative counter is disabled (EM = "0" or respectively EA = "0") for the main, respectively auxiliary counter.
PA registers. The fAUX signal can be used to verify the divide ratio of the Auxiliary divider. If T1 = High and T0 = High, the lock output is configured as fMAIN. The signal is the buffered output of the MAIN divider. The fMAIN signal appears as normally high and pulses low whenever the divider reaches terminal count from the value programmed into the NM1, NM2 or NM3 registers. The fMAIN signal can be used to verify the divide ratio of the MAIN divider and the prescaler.
Test Modes
The lock output is selectable as fREF, fAUX, fMAIN and lock. Bits T1 and T0 of the E word control the selection (see Figures 6 and 10). If T1 = T0 = Low, or if the E-word is not sent, the lock output is configured as the normal lock output described in the Lock Detect section. If T1 = Low and T0 = High, the lock output is configured as fREF. The signal is the buffered output of the reference divider NR and the 3-bit binary counter SM. The fREF signal appears as normally low and pulses high whenever the divider reaches terminal count from the value programmed into the NR and SM registers. The fREF signal can be used to verify the divide ratio of the Reference divider. If T1 = High and T0 = Low, the lock output is configured as fAUX. The signal is normally high and pulses low whenever the divider reaches terminal count from the value programmed into the NA and
1996 Aug 6
14
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
Test Pin
The Test pin, Pin 19, is a buffered logic input which is exclusively ORed with the output of the prescaler. The output of the XOR gate is the input to the MAIN divider. The Test pin must be connected to VDD during normal operation as a synthesizer. This pin can be used as an input for verifying the divide ratio of the MAIN divider; while in this condition the input to the prescaler, RFIN, may be connected to VCCP through a 10k resistor in order to place prescaler output into a known state.
MAIN DIVIDER REF DIVIDER AUX DIVIDER MAIN AUX T1 T0 SELECT LOGIC
SM
LOCK
SR00609
Figure 10. Test Mode Diagram
PIN FUNCTIONS
PIN PIN DC V No. MNEMONIC 1 2 3 19 CLOCK DATA STROBE TEST -- -- 16 -- --
VSS VCCP = 3V 1
EQUIVALENT CIRCUIT
VDD
PIN PIN DC V No. MNEMONIC 9 RA 1.35
EQUIVALENT CIRCUIT
VDDA = 3V
RN
1.35
9
25A
17
RF
1.35
VSSA
11
PHA
--
5
RFIN
2.1
5 6
VDDA
13
PHI
--
2.5k 2.5k
11
6
RFIN
2.1
14
VSS VDDA = 3V
PHP
--
VSSA
VDD
8
REFIN
1.8
ENABLE 10 100k
18
LOCK
--
18
10
AUXIN
1.8
VSS VSS
SR00610
Figure 11. Pin Functions
1996 Aug 6
15
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
TYPICAL PERFORMANCE CHARACTERISTICS
11 8.5 8 10 VCCP = VDDA = VDD EM = EA = 1, Note5 9 I TOTAL (mA) I TOTAL (mA) 7.5 7 6.5 6 5.5 t = -40C t = 25C t = 85C 5 4.5 4 2.7 t = -40C t = 25C t = 85C VCCP = VDDA = VDD EA=0, EM=1, Note5
8
7
6
5 2.7
3.5
4.5
5.5
3.5
4.5
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SR00611
SR00614
Figure 12. Operational Supply Current vs Supply Voltage and Temperature
7
Figure 15. Main Operational Supply Current vs Supply Voltage and Temperature
3.5
6
VCCP = VDDA = VDD EA=0, EM=1, Note5 3
VDD = 3V, VDDA = 5V Pin = -10dBm, ref divider halted
5 I TOTAL (mA) I TOTAL (mA) 2.5
4
2 t = -40C t = 25C t = 85C
3 t = -40C t = 25C t = 85C
2
1.5
1 2.7 3.5 4.5 5.5 SUPPLY VOLTAGE (V)
1 50 100 AUXILIARY INPUT FREQUENCY (MHz) 150
SR00612
SR00615
Figure 13. Auxiliary Operational Supply Current vs Supply Voltage and Temperature
20
Figure 16. Auxiliary Operational Supply Current vs Frequency and Temperature
20
0 INPUT POWER (dBm)
VDD = VCCP 2.7V 3.5V INPUT POWER (dBm)
0 t=-40C t=25C t=85C
-20
4.5V 5.5V
-20
-40
TA = 25C, N = 3971.625
-40
VDD = VCCP = 3V N=3971.625
-60 1100 1000 1050 1150 500 550 600 650 700 750 800 850 900 950
-60 1100 1000 1050 1150 500 550 600 650 700 750 800 850 900 950
FREQUENCY (MHz)
SR00613
FREQUENCY (MHz)
SR00616
Figure 14. Main Divider Input Power vs frequency and Supply
Figure 17. Main Divider Input Power vs Frequency and Temperature
1996 Aug 6
16
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
0 5 VDD= 3V, MINIMUM INPUT POWE (dBm) 0 VDDA= 5V, N = 100
-5 INPUT POWER (dBm)
-10
-5
-15 VDD/VDDA -20 3/3V 3/5V 5/5V N=100 -30 10 15 20 25 30 35 40 45 50 55 FREQUENCY (MHz)
-10 t = -40C t = 25C t = 85C
-25
-15
-20 10 15 20 25 30 35 40 FREQUENCY (dBm)
SR00617
SR00631
Figure 18. Reference Divider Minimum Input Power vs frequency and Supply
0 VDD/VDDA -5 MINIMUM INPUT POWER (dBm) TA =amb, PA=1, N=100 3/3V 3/5V 5/5V
Figure 21. Reference Divider Minimum Input Power vs Frequency and Temperature
-10 VDD =3V, MINIMUM INPUT POWER (dBm) VDDA=5V, PA=1, N=100 -15 t = -40C t = 25C t = 85C
-10
-15
-20
-20
-25
-30 30 50 70 90 110 FREQUENCY (MHz) 130 150
-25 30 50
SR00618
70 FREQUENCY (MHz)
90 SR00632
Figure 19. Auxiliary Divider Minimum Input Power vs Frequency and Supply
0 TA = amb, PA=0, N=25 VDD/VDDA
Figure 22. Auxiliary Divider Minimum Input Power vs Frequency and Temperature
0 VDD=3V, MINIMUM INPUT POWER (dBm) VDDA=5V -5 PA=0, N=25
-5 MINIMUM INPUT POWER (dBm)
-10
t = -40C t = 25C t = 85C
-15 3/3V 3/5V 5/5V
-10
-20
-15
-25
-30 50 100 150 FREQUENCY (MHz) 200 250
-20 50 100 150 FREQUENCY (MHz) 200
SR00619
Figure 20. Auxiliary Divider Minimum Input Power vs Frequency and Supply
Figure 23. Auxiliary Divider Minumum Input Power vs Frequency and Temperature
1996 Aug 6
17
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
j1
j0.5
j2
VCCP = VDD = 3V TA = 25C
R3 1 1
L4 2nH
0 50
C2 0.1pF
R1 3000
C1 0.85pF
300
600 900
Equivalent Input Impedance
1100
-j0.5
-j2
-j1
SR00620
Figure 24. Typical RFIN Input Impedance
1996 Aug 6
18
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
TOP SILK SCREEN
TOP VIEW
BOTTOM VIEW Figure 25. SA7025DK Demoboard Layout (NOT ACTUAL SIZE)
SR00621
1996 Aug 6
19
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
SR00622
Figure 26. SA7025DK Application Circuit
1996 Aug 6
20
Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
1996 Aug 6
21
Philips Semiconductors
Product specification
Low-voltage 1GHz fractional-N synthesizer
SA7025
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. print code Document order number:
Philips Semiconductors

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